Information handling system including a circuitized substrate having a dielectric layer without continuous fibers

ABSTRACT

An information handling system which includes as part thereof a circuitized substrate comprising a first layer comprised of a dielectric material including a resin material including a predetermined quantity of particles therein and not including continuous fibers, semi-continuous fibers or the like as part thereof, and at least one circuitized layer positioned on the dielectric first layer.

CROSS-REFERENCE TO CO-PENDING APPLICATIONS

This application is a divisional of Ser. No. 10/812,890, entitled “Circuitized Substrate, Method of Making Same, Electrical Assembly Utilizing Same, and Information Handling System Utilizing Same”, and filed Mar. 31, 2004. Ser. No. 10/812,890 is now U.S. Pat. No. 7,078,816, having issued Jul. 18, 2006.

TECHNICAL FIELD

This invention relates to circuitized substrates and particularly to those used in multilayered circuit boards, chip carriers, and the like, and to processes for manufacturing same. More particularly, the invention relates to substrates used in such final products so as to provide same with increased circuit density, particularly where such final products are information handling systems.

BACKGROUND OF THE INVENTION

Multilayered printed circuit boards (PCBs), laminate chip carriers, and the like permit formation of multiple circuits in a minimum volume or space. These typically comprise a stack of layers of signal, ground and/or power planes (lines) separated from each other by a layer of dielectric material. The lines are often in electrical contact with each other by plated holes passing through the dielectric layers. The plated holes are often referred to as “vias” if internally located, “blind vias” if extending a predetermined depth within the board from an external surface, or “plated-thru-holes” (PTHs) if extending substantially through the board's full thickness. By the term “thru-hole” as used herein is meant to include all three types of such board openings.

Conventional methods for fabricating PCBs, chip carriers and the like typically comprise fabrication of separate innerlayer circuits (circuitized layers), which are formed by coating a photosensitive layer or film over a copper layer of a copper clad innerlayer base material. The photosensitive coating is imaged, developed and the exposed copper is etched to form conductor lines. After etching, the photosensitive film is stripped from the copper leaving the circuit pattern on the surface of the innerlayer base material. This processing is also referred to as photolithographic processing in the PCB art and further description is not deemed necessary.

Following the formation of individual innerlayer circuits, a multilayer stack is formed by preparing a lay-up of innerlayers, ground planes, power planes, etc., typically separated from each other by a dielectric pre-preg typically comprising a layer of glass (typically fiberglass) cloth impregnated with a partially cured material, typically a B-stage epoxy resin. The top and bottom outer layers of the stack usually comprise copper clad, glass-filled, epoxy planar substrates with the copper cladding comprising exterior surfaces of the stack. The stack is laminated to form a monolithic structure using heat and pressure to fully cure the B-stage resin. The stack so formed typically has metal (usually copper) cladding on both of its exterior surfaces. Exterior circuit layers are formed in the copper cladding using procedures similar to the procedures used to form the innerlayer circuits. A photosensitive film is applied to the copper cladding. The coating is exposed to patterned activating radiation and developed. An etchant is then used to remove copper bared by the development of the photosensitive film. Finally, the remaining photosensitive film is removed to provide the exterior circuit layers.

Electrically conductive thru-holes (or interconnects) are used to electrically connect individual circuit layers within the structure to each other and to the outer surfaces and typically pass through all or a portion of the stack. Thru-holes are generally formed prior to the formation of circuits on the exterior surfaces by drilling holes through the stack at appropriate locations. Following several pre-treatment steps, the walls of the holes are catalyzed by contact with a plating catalyst and metallized, typically by contact with an electroless or electrolytic copper plating solution to form conductive pathways between circuit layers. Following formation of the conductive thru-holes, exterior circuits, or outerlayers are formed using the procedure described above.

After construction, chips and/or other electrical components are mounted at appropriate locations on the exterior circuit layers of the multilayered stack, typically using solder mount pads to bond the components to the PCB. The components are often in electrical contact with the circuits within the structure through the conductive thru-holes, as desired. The solder pads are typically formed by coating an organic solder mask coating over the exterior circuit layers. The solder mask may be applied by screen coating a liquid solder mask coating material over the surface of the exterior circuit layers using a screen having openings defining areas where solder mount pads are to be formed. Alternatively, a photoimageable solder mask may be coated onto the board and exposed and developed to yield an array of openings defining the pads. The openings are then coated with solder using processes known to the art such as wave soldering.

Complexity of the resulting products as described herein has increased significantly over the past few years. For example, PCBs for mainframe computers may have as many as 36 layers of circuitry or more, with the complete stack having a thickness of about 0.250 inch (250 mils). These boards are typically designed with three or five mil wide signal lines and twelve mil diameter thru-holes. For increased circuit densification in many of today's products such as PCBs, chip carriers and the like, the industry desires to reduce signal lines to a width of two mils or less and thru-hole diameters to two mils or less. Most known commercial procedures, especially those of the nature described herein, are incapable of economically forming the dimensions desired by the industry.

In addition to decreasing line width and via diameter, the industry also desires to avoid manufacturing problems frequently associated with PCBs, chip carriers and the like. As described above, current procedures utilize innerlayer materials that are glass-reinforced resin or other suitable dielectric material layers having a thickness of from about two to five mils clad with metal (typically copper) on both surfaces. Glass-reinforcing material, typically utilizing continuous strands of fiberglass which extend throughout the width and length of the overall final substrates used, is used to contribute strength and rigidity to the final stack. Being continuous, these strands run the full width (or length) of the structure and include no breaks or other segments as part thereof. As such, these occupy a relatively significant portion of the substrate's total volume, a disadvantage especially when attempting to produce highly dense numbers of thru-holes and very fine line circuitry to meet new design requirements. Specifically, when holes are drilled (using laser or mechanical drills) to form thru-holes, the fiberglass fibers can extend into the holes and, if so, must be removed prior to metallization. Removal creates the need for additional pretreatment steps such as the use of glass etchants to remove glass fibrils extending into the holes. If the glass is not removed, a loss of continuity might occur in the metal deposit. In addition, the continuous glass fibers add weight and thickness to the overall final structure.

Additionally, since lamination is typically at a temperature above 150° C., the resinous portion of the laminate shrinks during cooling to the extent permitted by the rigid copper cladding, which is not the case for the continuous strands of fiberglass or other continuous reinforcing material used. The strands thus take on a larger portion of the substrate's volume following such shrinkage and add further to complexity of manufacture in a high density product. If the copper is etched to form a discontinuous pattern, laminate shrinkage may not be restrained even to the extent above by the copper cladding. Obviously, this problem is exacerbated as feature sizes (line widths and thicknesses, and hole diameters) decrease. Consequently, further shrinkage may occur. The shrinkage, possibly in part due to the presence of the relatively large volume percentage of continuous fiber strands in the individual layers used to form a final product possessing many such layers, may have an adverse affect on dimensional stability and registration between said layers, adding even more problems to the PCB manufacturer.

Furthermore, the presence of glass fibers, especially woven glass fibers, substantially impairs the ability to form high quality, very small thru holes using a laser. Glass cloth has drastically different absorption and heat of ablation properties than any thermoset or thermoplastic matrix resin. In a typical woven glass cloth, the density of glass a laser might encounter can vary from approximately 0% in a window area to approximately 50% by volume (or more) in an area over a cloth knuckle. This wide variation in encountered class density leads to problems obtaining the correct laser power for each hole and results in wide variation in hole quality

Furthermore, the presence of glass fibers greater contributes to an electrical failure mode known as CAF. CAF (cathodic/anodic filament growth) is an electrical shorting failure which occurs when dendritic metal filaments grow along an interface (typically a glass fiber/epoxy resin interface), creating an electrical path between two features which should remain electrically isolated. Whether continuous (like woven cloth) or semi-continuous (like chopped fiber mattes), glass fiber lengths are substantial in comparison to the common distances between isolated internal features, thus glass fibers can be a significant detractor for PCB insulation resistance reliability. While use of glass mattes composed of random discontinuous chopped fibers can largely abate the problem of laser drilled hole quality, because such mattes still contain fibers with substantial length compared to internal board feature spacings, use of the glass fiber containing mattes offer no relief form the problem of CAF.

One improvement in the manufacture of products such as PCBs is described in U.S. Pat. No. 5,246,817. In accordance with this '817 patent, the manufacturing process consists of the sequential formation of layers using photosensitive dielectric coatings and selective metal deposition procedures. The first layer of the board is formed over a temporary or permanent carrier that may become an integral part of the board. When the carrier is a circuit, the process comprises formation of a dielectric coating over the circuit with imaged openings defining the thru-holes. The imaged openings may be obtained by exposure of a photosensitive dielectric coating to activating radiation through a mask in an imaged pattern followed by development to form the imaged openings. Alternatively, imaging may be by laser ablation in which case, the dielectric material need not be photosensitive. Metal is deposited into the recesses within the dielectric coating to form the conductive thru-holes. Thereafter, an additional layer of dielectric is coated onto the first dielectric layer, imaged in a pattern of circuit lines, and the recesses are then plated with metal. Alternatively, after imaging the first dielectric coating, it may be coated with a second dielectric coating and imaged and the recesses plated with metal to form the thru-holes and circuit lines simultaneously. By either process, the walls of the imaged opening or recesses in the dielectric coating contain metal as it deposits during plating and assures a desired cross-sectional shape of the deposit. Plating desirably fills the entire recess within the imaged photosensitive coating. The process, obviously very complex and costly, is repeated sequentially to form sequential layers of circuits and thru-holes.

Another example of a PCB with a specific dielectric material composition is described in U.S. Pat. No. 6,207,595 in which the dielectric layer's fabric material is made from a cloth member having a low enough content of particulates and a sufficient quantity of resin material to completely encase the cloth member including the particulates, so that the resin material extends beyond the highest protrusions of the cloth member (i.e. the fabric material is thicker and will pass a certain test standard (in '595, the known HAST level A test). Thus, the woven cloth is known to include a quantity of particulates, which term is meant in '595 to include dried film, excess coupler, broken filaments, and gross surface debris. A process is described where a sizing of polyvinyl alcohol, corn starch and a lubricant of oil is applied to the strands of fiber prior to weaving in order to improve the weaving process and minimize breakage of the strands. After weaving, the sizing is removed by a firing step to clean the filaments of lubricants and other materials. However, some sizing is randomly left behind as particulates. Encasing the woven cloth including the particulates is a quantity of hardened resin material. The resin may be an epoxy resin such as one often used for “FR4” composites (“FR4” has become a conventional, abbreviated name for the resulting substrates and often also for the resins forming part thereof, and is based in part on the flame retardant (hence the “FR” designation) rating of these established products. A resin material based on bismaleimide-triazine (BT) is also acceptable for the structure in this patent. More preferably, the resin is a phenolically hardenable resin material known in the PCB industry. This patent thus requires continuous fibers (those extending across the entire width (or length) of the dielectric layer except for possible inadvertent interruptions caused by drilling of the thru-holes needed in the final product, causing these fibers to become what might be called as “broken.” The aforementioned problem with fiber strands exposed to the holes is thus possible in this patent's process and resulting structure.

In U.S. Pat. No. 5,418,689, there is described a PCB product wherein the dielectric substrate can include a thermoplastic and/or thermosetting resin. Thermosetting polymeric materials mentioned in this patent include epoxy, phenolic base materials, polyimides and polyamides. Examples of some phenolic type materials include copolymers of phenol, resorcinol, and cresol. Examples of some suitable thermoplastic polymeric materials include polyolefins such as polypropylene, polysulfones, polycarbonates, nitrile rubbers, ABS polymers, and fluorocarbon polymers such as polytetrafluoroethylene, polymers of chlorotrifluoroethylene, fluorinated ethylenepropylene polymers, polyvinylidene fluoride and polyhexafluoropropylene. The dielectric materials may be molded articles of the polymers containing fillers and/or reinforcing agents such as glass filled polymers. “FR4” epoxy compositions that are employed in this patent contain 70-90 parts of brominated polyglycidyl ether of bisphenol-A and 10-30 parts of tetrakis (hydroxyphenyl) ethane tetraglycidyl ether cured with 3-4 parts of dicyanodiamide, and 0.2-0.4 parts of a tertiary amine, all parts being parts by weight per hundred parts of resin solids. Another “FR4” epoxy composition may contain about 25 to about 30 parts by weight of a tetrabrominated diglycidyl ether of bisphenol-A having an epoxy equivalent weight of about 350 to about 450; about 10 to about 15% by weight of a tetrabrominated glycidyl ether of bisphenol-A having an epoxy equivalent weight of approximately 600 to about 750 and about 55 to about 65 parts per weight of at least one epoxidized nonlinear novolak having at least 6 terminal epoxy groups; along with suitable curing and/or hardening agents. A still further “FR4” epoxy composition contains 70 to 90 parts of brominated polyglycidyl ether of bisphenol-A and 10 to 30 parts of tetrakis (hydroxyphenyl) ethane tetraglycidyl ether cured with 0.8-1 phr of 2-methylimidazole. Still other “FR4” epoxy compositions employ tetrabromobisphenol-A as the curing agent along with 2-methylimidazole as the catalyst.

In U.S. Pat. No. 6,323,436, PCBs are prepared by first impregnating a non-woven aramid chopped fiber mat or a thermoplastic liquid crystalline polymer (LCP) paper instead of the reinforcement typically used in the electronics industry, described in this patent as a woven glass fabric. The aramid reinforcement is comprised of a random (in-plane) oriented mat of p-aramid (poly(p-phenylene terephthalamide) fibers comprised of Kevlar (Kevlar is a registered trademark of E. I. DuPont de Nemours and Company), and has a dielectric constant of 4.0 as compared to 6.1 for standard E-glass cloth. The lower permittivity of the non-woven aramid reinforcement provides for faster signal propagation, allowing increased wiring density and less crosstalk, which becomes increasingly important for high I/O chips and miniaturization. Since the p-aramid fibers are transversely isotropic and have an axial CTE of about −3 to about −6 ppm/degree C. below the glass transition temperature when combined with a thermosetting resin, the final composite described in this patent is said to possess a CTE which can be controlled and adjusted to match that of silicon or semiconductor chips in the range of about 3 to about 10 ppm/degree C. The thermoplastic liquid crystal polymer paper is a material called Vecrus (Vecrus is a registered trademark of Hoechst Celanese Corp.). LCP paper uses the company's Vectra polymer (Vectra also being a registered trademark of Hoechst Celanese Corp.). According to this patent, it has a dielectric constant of 3.25 and a dissipation factor of 0.024 at 60 Hz. The polymer paper has a UL94-V0 rating and an in-plane CTE of less than 10 ppm/degree C. The alleged advantages of this material over the aramid mat are the lower dielectric constant and very low moisture absorption, less than 0.02%. The non-woven aramid or LCP paper is used in conjunction with a thermosetting resin to form the final composite substrate. Examples of thermosetting resins described as being useful in this patent include epoxy, cyanate ester, bismaleimide, bismaleimide-triazine, maleimide or combinations thereof. The resin-impregnated low CTE reinforcement is then partially cured to a “B”-stage to form the prepreg, and then the prepreg is cut, stacked, and laminated to form a subcomposite with exterior copper sheets.

Another form of dielectric materials known for use in circuitized substrates include those known as “expanded PTFE” materials, PTFE of course being the designate for polytetrafluoroethylene. A more common example of such material is the aforementioned Teflon, sold by E. I. DuPont de Nemours and Company. In U.S. Pat. No. 5,652,055, for example, there is described an adhesive sheet (or “bond film”) material suitable to serve as adhesive layers in a variety of adhesive applications, such as in circuit board laminates, multi-chip modules, and in other electrical applications. The adhesive sheet is described as being constructed from an expanded polytetrafluoroethylene (PTFE) material, such as that taught in U.S. Pat. No. 3,953,566. Preferably, the material is filled with an inorganic filler and is constructed as follows. A ceramic filler is incorporated into an aqueous dispersion of dispersion-produced PTFE. The filler in small particle form is ordinarily less than 40 microns in size, and preferably less than 15 microns. The filler is introduced prior to co-coagulation in an amount that will provide 10 to 60%, and preferably 40 to 50% by weight filler in the PTFE, in relation to the final resin-impregnated composite. The filled PTFE dispersion is then co-coagulated, usually by rapid stirring. The coagulated filled PTFE is then added. The filled material is then lubricated with a common paste extrusion lubricant, such as mineral spirits or glycols, and then paste extruded. The extrudate is usually calendared, and then rapidly stretched to 1.2 times to 5000 times, preferably 2 times to 100 times, per this patent, at a stretch rate of over 10% per second at a temperature of between 35 degrees C. and 327 degrees C. The lubricant can be removed from the extrudate prior to stretching, if desired. The resulting expanded, porous filled PTFE is then imbibed with adhesive by dipping, calendaring, or doctor blading on a varnish solution of about 2% to 70% adhesive in solvent. The wet composite is then affixed to a tenter frame, and subsequently B-staged at or about 165 degrees C. for 1 to 3 minutes. The resulting sheet adhesive thus obtained typically consists of: (a) 9 to 65 weight percent PTFE; (b) 9 to 60 weight percent inorganic filler, in the form of particulate; and (c) 5 to 60 weight percent adhesive imbibed within the porous structure of the filled PTFE web.

Various other types of expanded-PTFE substrate materials are described in the aforementioned U.S. Pat. No. 3,953,566, and also in U.S. Pat. Nos. 4,187,390 and 4,482,516, as well as others. U.S. Pat. No. 4,187,390 is particularly interesting because it delves substantially into both nodes and fibrils used as part of such substrate materials, breaking these down into such dimensional constraints as node height, node width, node length, and fibril length.

Still other examples of methods of making circuitized substrates such as PCBs are described and illustrated in the following documents:

3,962,653 Basset 4,579,772 Bhatt et al 4,642,160 Burgess 4,675,789 Kuwabara et al 4,713,137 Sexton 4,783,345 Kleeberg et al 4,864,722 Lazzarini et al 5,129,142 Bindra et al 5,229,550 Bindra et al 5,368,921 Ishii et al 5,376,453 von Gentzkow et al 5,483,101 Shimoto et al 5,565,267 Capote et al 5,648,171 von Gentzkow et al 5,670,262 Dalman 5,677,045 Nagai et al 5,685,070 Alpaugh et al 5,726,863 Nakayama et al 5,814,405 Branca et al 5,981,880 Appelt et al 6,018,196 Noddin 6,042,685 Shinada et al 6,119,338 Wang et al 6,143,401 Fischer 6,212,769 B1 Boyko et al 6,248,959 B1 Sylvester 6,291,779 B1 Lubert et al 6,378,201 B1 Tsukada et al 6,405,431 B1 Park et al 6,506,979 B1 Shelnut et al 6,541,589 B1 Baillie 6,586,687 B2 Lee et al US2002/0150673 Thorn et al US2002/0170827 Furuya US2002/0172019 Suzuki et al US2002/0190378 Hsu et al US2003/0022013 Japp et al JP 56049271 Nishikawa et al JP 7086710 Nagai et al JP 7097466 Azuma et al JP 8092394 Yonekura et al JP2001015912A2 Koji JP2002223070A2 Koji et al

As described herein, the present invention represents a significant improvement over processes such as those above in the production of circuitized substrates such as PCBs. One particularly significant feature of this invention is the provision of a dielectric material which includes a resin and certain particles, but does not include continuous glass fibers or the like as part thereof. As stated, such continuous length fibers have heretofore been deemed necessary to provide sufficient strength in the resulting dielectric layer of many substrate dielectric materials to stand subsequent processing (especially the strenuous pressures and temperatures of lamination) of the layers into a final, multilayered structure. Elimination of continuous, or substantially continuous, lengthy strands of these materials, coupled with use of particles, facilitates hole formation and thus enhances the opportunities for reduced line widths and thicknesses, satisfying design requirements for greater board densities.

It is believed that such an invention will represent a significant advancement in the art.

OBJECTS AND SUMMARY OF THE INVENTION

It is a primary object of the invention to enhance the art of circuitized substrates.

It is another object to provide a new and unique method of making a circuitized substrate which is adaptable to current manufacturing procedures and which is accomplished by more simplified usage thereof to thereby result in a product of reduced cost.

According to one embodiment of the invention, there is provided a circuitized substrate comprising a first layer comprised of a dielectric material including a resin material including a predetermined quantity of particles therein and not including continuous fibers, semi-continuous fibers or the like as part thereof and at least one circuitized layer positioned on the first layer.

According to another embodiment of the invention, there is provided an electrical assembly comprising a circuitized substrate including a first layer comprised of a dielectric material including a resin material including a predetermined quantity of particles therein and not including continuous fibers, semi-continuous fibers or the like as part thereof, and at least one circuitized layer positioned on the first layer, and at least one electrical component positioned on and electrically coupled to the circuitized substrate.

According to yet another embodiment of the invention, there is provided a method of making a circuitized substrate, the method comprising providing a first layer comprised of a dielectric material including a resin material including a predetermined quantity of particles therein and not including continuous fibers, semi-continuous fibers or the like as part thereof, and positioning at least one circuitized layer on the first layer of dielectric material.

According to still another embodiment of the invention, there is provided a multilayered circuitized structure comprising a first circuitized substrate portion including a first layer including a dielectric material having a resin material including a predetermined quantity of particles therein and not including continuous fibers, semi-continuous fibers or the like as part thereof, and at least one circuitized layer positioned on the first layer, the first circuitized substrate having a first pattern of interconnecting conductive thru-holes therein of a first density. The structure further includes second and third circuitized substrate portions positioned on opposite sides of the first circuitized substrate portion, each having a second pattern of interconnecting thru-holes therein and of a density less dense than the first density of interconnecting conductive thru-holes of the first circuitized substrate portion. The first circuitized substrate portion provides electrical interconnection between the second and third circuitized substrate portions.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1-6 represent some of the steps utilized to produce a circuitized substrate in accordance with a preferred embodiment of the invention, FIGS. 3-6 being on a larger scale than those of FIGS. 1 and 2; and

FIG. 7, on a much smaller scale than FIGS. 1 and 2, illustrates an electrical assembly which may utilize one or more of the circuitized substrates defined herein and made in accordance with the teachings herein.

BEST MODE FOR CARRYING OUT THE INVENTION

For a better understanding of the present invention, together with other and further objects, advantages and capabilities thereof, reference is made to the following disclosure and appended claims in connection with the above-described drawings.

“Information handling system” as used herein shall mean any instrumentality or aggregate of instrumentalities primarily designed to compute, classify, process, transmit, receive, retrieve, originate, switch, store, display, manifest, measure, detect, record, reproduce, handle or utilize any form of information, intelligence or data for business, scientific, control or other purposes. Examples include personal computers and larger processors such as computer servers and mainframes. Such products are well known in the art and are also known to include PCBs and other forms of circuitized substrates as part thereof, some including several such components depending on the operational requirements thereof.

FIG. 1 illustrates an initial step in forming a circuitized substrate as defined herein. As understood from the following, a key attribute of the present invention is the utilization of a dielectric material as part of the substrate which enables the provision of high density arrays of thru-holes within the substrate while preventing electrical shorting or the like between closely spaced, adjacent holes. That is, very highly dense concentrations of relatively narrow (in diameter) thru-holes are capable of being provided in this unique dielectric layer which can then be rendered conductive (typically, plated) to provide highly dense circuit connections between designated conductive layers (e.g., signal, power and/or ground) within the final structure incorporating the circuitized substrate. Most significantly, this new dielectric material does not include continuous fibers such as fiberglass fibers required in so many known dielectric layers, the most well known of same being the aforementioned “FR4” material. As explained, use of such fibers is often deleterious when producing substrates during the hole forming and plating stages because of fiber or its material intrusion within the holes which can form a base for a conductive path to adjacent conductive holes. A singular electrical short of this type can render a final PCB or chip carrier inoperative for its intended purpose, a costly manufacturing expense. The unique material taught herein is able to overcome this deficiency while assuring relatively high dielectric reliability and a relatively thin final layer, both highly desirable if the final product (e.g., chip carrier or PCB) using the substrate is to meet many of today's high density requirements.

The dielectric material used to form the circuitized substrate of the invention utilizes a resin material in combination with a predetermined volume of fine particles, the latter preferably comprised of silica and/or ceramic materials. In a preferred embodiment, the dielectric resin is a high Tg DICY free epoxy such as Huntsman LZ-8213, available from Huntsman Advanced Materials in Brewster, N.Y. Optionally, a high molecular weight reactive thermoplastic resin such as Inchem PKHS-40, available from InChem Corporation in Rock Hill, S.C., can also be added to impart toughness and coating flake-off resistance. Tatsumori PLV-6 spherical amorphous silica is added to control CTE. This silica is available from Tatsumori, Ltd., Tokyo, Japan (represented by Tatsumori U.S.A., Inc., New York, N.Y.). The spherical nature of this filler allows high volumetric loading of filler without driving the melt viscosity of the coating too high to preclude ordinary lamination processing such as that used for FR-4. Optionally, a thixotrope such as Degussa R-972, available from Degussa Corporation, Pigments Division, Teterboro, N.J., can be added to achieve an improved balance between the solution viscosity of the solvent containing coating varnish and the melt viscosity of the B-staged dielectric coating. Suitable catalysts for the epoxy include amines such as the imidazoles, tertiary amines such as benzyldimethylamine, 1.3-tetramethyl butane diamine, tris (dimethylaminomethyl) phenol, pyridine, and triethylenediamine, and acidic catalysts, such as stannous octoate. A solvent such as M.E.K., available from Brand Nu Laboratories, Meriden, Conn., is added to dissolve the various resins and permit coating of the film carrier. Optionally a silane such as Dow-Corning Z-6040, available from Dow-Corning Corporation, Midland, Mich., can be added to improve filler to resin interfacial adhesion.

Particle composition by volume ranges from about 10 percent by volume to about 80 percent by volume of the total volume of the dielectric layer. A preferred particle volume for a dielectric layer taught herein is about 39 percent. As such, the particles each have a size within the range of about 200 Angstroms to about 35 microns, a preferred size being about 10 microns. The above ranges are not meant to limit the invention, as others are acceptable for use in the present invention. Other thermally conductive and electrically insulating fillers could be used for improving the thermal heat transfer from the device to the surroundings. Such fillers include aluminum oxide, 92% alumina, 96% alumina, aluminum nitride, silicon nitride, silicon carbide, beryllium oxide, boron nitride and diamond powder (made from either the high pressure or Plasma CVD process. Especially preferred fillers are aluminum oxide and aluminum nitride because of their high thermal conductivity.

The preferred filler can be optionally pre-treated with a coupling agent, such as γ amino propyl triethoxy silane (A1100) or β-(3,4-epoxy cyclohexyl) ethyltrimethoxy silane (A186), or γ-glycidylpropyltrimethoxy silane (Z6040) from Dow-Corning. An amount of coupling agent which is about 0.25% by weight of filler has been found to be satisfactory. The amount can be determined by weight loss of filler treated with coupler after burning. The amount should not be more than about a few monolayers. The particles as used provide reinforcement for the final layer in comparison to a resin material not including same. Of further significance, the particles assure a finished composite structure which has a relatively low isotropic expansion in the 20-25 ppm (parts per million)/degrees Celsius (C.) thermal expansion range. Further, the particles provide fracture and fatigue resistance, relatively low moisture absorption and a roughened surface texture sufficient to facilitate subsequent plating (especially with copper) on the formed thru-hole and other, e.g., external, surfaces. The addition of specific volume percentages of particles thus allows the product manufacturer to adjust the coefficient of thermal expansion (CTE). The following represents a chart showing the relative CTE values for dielectric layers formed when using the aforedefined resin material and the corresponding percentages by weight of the identified particles.

Particle Material Particle Size Volume Fraction CTE Spherical Amorphous Silica 2-15 μm 39% 35 Spherical Amorphous Silica 2-15 45% 27 Spherical Amorphous Silica 2-15 30% 70 Hollow Silica Microspheres 5-32 μm 39% 35 Alumina 2-15 μm 39% 50 Boron Nitride 2-15 μm 39% 50 Titania 2-15 μm 39% 50

It has been discovered that when drilling (e.g., typically using a laser, described below) thru-holes in the above material, highly dense concentrations of such hole patterns is attainable without electrical shorting of the holes after being plated (made conductive). That is, the plating material (typically copper) does not migrate from thru-hole to thru-hole, as occasionally occurred when fiberglass and other fibrous materials were utilized.

Dielectric layers produced using the above materials possess the following key electrical, thermal, physical and thermal expansion properties. Physical modeling and process development activities determined that the following properties with specified desired targets and permissible ranges.

Desired Range Electrical properties Dk (dielectric constant) @ 1-2.5 GHz 3.77 3.5-4.0 (average) Loss factor at 1 MHz 0.0130  0.01-0.028 Thermal properties Tg (DSC mid point) (deg C.) 178 165-180 Tg (TMA) (deg C.) 174 165-180 Decomposition Temperature (deg C.) 317 300-330 Physical properties % moisture, 24 hr RT 0.18 0.01 to 0.30 % moisture 1 hr, PCT 0.44 0.3 to 0.5 Modulus (M psi) 1.2 0.8 to 1.5 Elongation (%) 2.0 1-3 Thermal Expansion below Tg (x, y, z), (ppm/C. isotropic) 31 24-35 above Tg (x, y, z), (ppm/C. isotropic) 111  90-120

In one embodiment of the invention, it was possible to drill a total of 10,000 holes within one square inch of dielectric layer, representing an extreme example of the high density hole patterns attainable using the unique teachings herein. Pattern densities ranging from about 5,000 holes per square inch to about 10,000 holes per square inch are readily attainable using the present invention's teachings. As stated, a laser is preferably used for such drilling, and in particular, a YAG laser, which is capable in one embodiment of the invention of providing about 50 thru-holes per second within the dielectric layer.

As further understood from the description herein, a particular use for the circuitized substrate formed herein is as part of a chip carrier or a PCB or other electronic packaging product such as those made and sold by the Assignee of the instant invention. One particular example is a chip carrier sold under the name Hyper-BGA chip carrier (Hyper-BGA being a registered trademark of Endicott Interconnect Technologies, Inc.). The invention is of course not limited to chip carriers or even to higher level PCBs. It is also understood that more than one such circuitized substrate (also referred to as a “core”, a specific example being what is referred to as a “power core” if the core includes one or more power planes and is thus to serve primarily in this capacity) may be incorporated within such a carrier or PCB, depending on operational requirements desired for the final product. As defined below, the “core” can be readily “stacked up” with other layers, including conductors and dielectric, and bonded together (preferably using conventional PCB lamination processing) to form the multilayered carrier or multilayered PCB. The laminate so formed is then subjected to further processing, including conventional photolithographic processing to form circuit patterns on the outer conductive layers thereof. As described hereinbelow, such external patterns can include conductive pads on which conductors such as solder balls can be positioned to connect the structure to other components such as semiconductor chips, PCBs and chip carriers if so desired. The unique teachings of this invention are thus adaptable to a multitude of electronic packaging products. Significantly, the invention enables incorporation of the circuitized substrate (e.g., if a dense “core”) with its highly dense thru-hole patterns and interconnection capabilities within a larger multilayered structure in which the other layered portions do not possess such densification and operational capabilities. Thus, a “standard” multilayered product can be produced for most of its structure and the unique subcomponent taught herein simply added in as part of the conventional processing of such a “standard”. If the circuitized substrate core is internally positioned, it enables highly dense connections between other, less dense portions of the multilayered product, thus giving said product the unique capabilities of the invention in at least a portion thereof.

In FIG. 1, an initial, preferred step in forming a circuitized substrate as taught herein, involves bringing together two layered members 11 and 11′. Each member preferably includes a relatively thin layer 13 of dielectric material having the composition defined herein and a conductive layer 15 (preferably copper) thereon. Layers 13 are each preferably of a thickness (T2) of about 1-4 mils (thousandths of an inch) with a preferred thickness being 2 mils (0.002 inch). Each conductive layer is even less in thickness (T1), within the range of only about 0.25 mils to about 1.5 mils thick. A preferred thickness is 0.5 mils. Each of the dielectric layers, including a resin as part of the composition, is preferably in what is known in the art as a “B-stage” state. Layered members 11 and 11′ are aligned and bonded together using conventional PCB lamination processing. In one example, a total pressure of about 400 pounds per square inch (PSI) was used, at a temperature of about 188 deg. C., for a period of about 90 minutes. The result is a laminated substrate 21 (FIG. 2) having outer conductive layers 15 each of substantially the same thickness as above but a common interim dielectric layer 13′ having a compressed thickness of about 4.2 mils, giving the overall final substrate a thickness (T3) of about 5.6 mils. The interim dielectric material 13′, as a result of such lamination, is now in what is referred to in the art as a “C-stage” state. This substrate will now serve to form the base for the circuitized substrate defined herein, which, as also defined, may serve as a “core” substrate for a thicker, multilayered product such as a PCB or chip carrier.

In FIG. 3, substrate 21 (now shown on a larger scale than in FIGS. 1 and 2 for illustration purposes) is now subjected to a conventional photolithographic step in which outer conductive layers 15 are “circuitized.” That is, layers 15 are processed using known processing to form a desired pattern thereon. This pattern will include, at a minimum, several openings 17 in each layer which are aligned opposite each other as shown. In addition, it is also within the scope of the invention to provide additional circuit features such a lines and/or pads 19 within one or both layers. If substrate 21 is to serve as a “power core”,layers 15 will typically only include openings 19 therein. However, if one or both layers 15 are to function in another capacity, e.g., as a signal layer, then other patterns may be provided. The patterns in FIG. 3 (and FIGS. 4-6) are thus not meant to limit the scope of the invention.

In FIG. 4, the substrate 21 is shown to include an additional layer 31 of dielectric material on opposite sides thereof, each layer preferably including a thin conductive (e.g., copper) layer 33 thereon. In one example of the invention, layers 31 and 33 are each comprised of the same materials and thicknesses as layers 13 and 15 in FIG. 1 and are laminated onto substrate 21 using lamination processes known in the art. Other acceptable layers for 13 and 15 contain a non-woven reinforcement based on duPont's Thermount aramid fiber matte paper. DriClad resin may be applied to Thermount using standard impregnation methods used to manufacture pre-preg. Other suppliers that provide resin coated Thermount include products from Shin-Kobe Electrical Machinery Co., Ltd., in Japan and Arlon, 55-LM, made by the Arlon Corporation, Engineered Laminates and Coatings Division in East Providence, R.I. Following lamination, each of the conductive layers 33 is “personalized” to include a plurality of openings 41 therein which align with respective ones of the openings 17 in the conductive layer 15 located adjacent thereto (but separated by the interim layer 31), as seen in FIG. 5. It is noteworthy that at least one opening 41 is aligned with a corresponding opening 17, but that other, perhaps smaller openings 41 may also be provided which are not so aligned, but instead align with other portions of the circuit formed on layer 15 (if one has been so formed). With openings 41 formed, thru-holes are drilled within the FIG. 5 structure using a laser of the type defined above. The laser drills thru-holes through the entire thickness of the FIG. 5 structure wherever paired, aligned openings 17 and corresponding aligned openings 41 are present, as seen in FIG. 6. In one embodiment, a total of 10,000 holes, each having a diameter of only about 2 mils, were provided in each square inch of the structure in these aligned orientations. This represents again the highly dense patterns attainable using the teachings of this invention.

In addition to the highly dense pattern of thru-holes 51 which extend through the entire thickness of the FIG. 5 structure, as seen in FIG. 6, lesser depth thru-holes 53 may also be formed simultaneously with the formation of holes 51 to reach only the conductive layer 15. The purpose of these latter holes is to eventually form an electrical connection with conductive layer 33 to layer 15, e.g., from selected signal lines on one to lines on another, again assuming layer 15 is also to function as a signal carrying conductive plane, adding greater versatility to the invention if so used. Layer 15 could also serve as a ground layer and thus providing grounding, if so desired. In addition, thru-holes 51 can be provided through the entire thickness (see FIG. 6) of the structure and only relative to (adjacent) a signal line or layer if layer 15 includes such lines or is entirely a signal plane, to thereby couple external signal layers such as 33 to selective internal signal lines and/or layers within the structure. It is understood that thru-holes 51 and 53 (if used) are then to be placed with conductive material, a preferred material being copper having a thickness of only about 0.5-0.75 mils. The preferred plating process may be either electrolytic or electroless, depending on the plating equipment available for such plating. Electrolytic and electroless plating of thru-holes is well known in the art (except for those having the relatively narrow diameters taught herein) so further description is not deemed necessary.

Also seen in FIG. 6 is the addition of yet another dielectric layer 71 (in phantom) on opposite sides of the structure formed with thru-holes therein, and an additional conductive layer 73 (also in phantom) on each of the dielectric layers. This represents the fact that several additional dielectric and conductive layers may be added to the FIG. 6 structure to form a larger multilayered final product such as a PCB or laminate chip carrier having more than the number of layers shown in FIGS. 3-6. Further, it is also possible to incorporate more than one such internal circuitized substrate “core” such as shown in FIG. 6 (or even in FIG. 3) within such a larger, thicker structure to thus afford the final structure with the teachings of the invention at more than one location therein. To this end, the embodiments of both FIG. 3 and the added layered embodiment of FIGS. 4-6 can be considered such “cores.”

FIG. 7 represents one example of an electrical assembly 81 that may be formed using the circuitized substrates taught herein. As stated, each substrate so formed in accordance with the teachings herein may be utilized within a larger substrate of known type such as a PCB, chip carrier or the like. FIG. 7 illustrates two of these larger components, one being a chip carrier 83 and the other a PCB 85. Obviously, PCB 85 is positioned within and electrically coupled to an electrical component (not shown) such as a personal computer, mainframe, server, etc. Chip carrier 83, as shown, is typically positioned on and electrically coupled to an underlying substrate such as PCB 85. Such a carrier also typically has a semiconductor chip 87 mounted thereon and also electrically coupled to the carrier. In the embodiment of FIG. 7, the connections between chip and carrier and between carrier and PCB are accomplished using solder balls 89 and 89′, respectively. Such connections are known in the art and further description is not considered necessary. The significance of FIG. 7 is to show the use of one or more of the circuitized substrates 91 (in phantom) of the invention in the chip carrier 83 and PCB 85, thus forming part thereof. Two substrates 91 are shown as used within PCB 85, while only one is shown within carrier 83. As mentioned above, the invention is not limited to the numbers shown. For example, three or more substrates 91, each forming a particular circuitized “core” (e.g., a “power core”) within the PCB, may be utilized to afford the PCB the highly advantageous teachings of the invention.

While there have been shown and described what are at present considered to be the preferred embodiments of the invention, it will be obvious to those skilled in the art that various changes and modifications may be made therein without departing from the scope of the invention as defined by the appended claims. 

1. An information handling system comprising as part thereof: a circuitized substrate including a first dielectric layer including an epoxy resin material and a filler comprising particles having a size within the range of from about 200 Angstroms to about 35 microns, said particles comprising from about 10 percent to about 80 percent by volume of said first dielectric layer, said first dielectric layer including reinforcing fibers, said fibers not including continuous or semi-continuous strands as part thereof, said first dielectric layer further including a plurality of conductive thru-holes therein having a pattern density of from about 5,000 to about 10,000 holes per square inch of said first dielectric layer, said first dielectric layer having a dielectric constant within the range of from about 3.5 to about 4.0, and at least one circuitized layer positioned on said first dielectric layer; and at least one electrical component positioned on and electrically coupled to said circuitized substrate.
 2. The information handling system of claim 1 wherein said epoxy resin of said first dielectric layer of said circuitized substrate is a high glass transition temperature, dicyandiamide-free epoxy resin.
 3. The information handling system of claim 2 wherein said first dielectric layer further includes a high molecular weight thermoplastic resin.
 4. The information handling system of claim 1 wherein said particles of said filler of said circuitized substrate comprise about 39 percent by volume of said first dielectric layer.
 5. The information handling system of claim 1 wherein the aspect ratio of the thickness of said circuitized substrate to the diameter of each of said thru-holes being within the range of from about 2:1 to about 20:1.
 6. The information handling system of claim 1 wherein said filler of said circuitized substrate comprising said particles comprises spherical amorphous silica having a particle size of from about 2 to about 15 microns.
 7. The information handling system of claim 1 wherein said filler of said circuitized substrate comprising said particles comprises aluminum oxide or aluminum nitride having a particle size of from about 2 to about 15 microns.
 8. The information handling system of claim 1 wherein said particles of said circuitized substrate include a coupling agent thereon having a thickness of no more than a few monolayers.
 9. The information handling system of claim 8 wherein said coupling agent is silane.
 10. The information handling system of claim 1 wherein said first dielectric layer of said circuitized substrate further includes a thixotrope.
 11. The information handling system of claim 1 wherein said at least one circuitized layer of said circuitized substrate comprises copper.
 12. The information handling system of claim 11 further including a second circuitized layer positioned on said first dielectric layer on a side opposite said at least one circuitized layer of said circuitized substrate.
 13. The information handling system of claim 12 wherein selected ones of said conductive thru holes of said circuitized substrate electrically couple selected parts of said at least one circuitized layer to selected parts of said second circuitized layer.
 14. The information handling system of claim 12 further including second and third dielectric layers positioned on said at least one circuitized layer and said second circuitized layer, respectively, of said circuitized substrate, and third and fourth circuitized layers formed on said second and third dielectric layer, respectively.
 15. The information handling system of claim 1 wherein said circuitized substrate comprises a chip carrier.
 16. The invention of claim 1 wherein said information handling system comprises a personal computer.
 17. The invention of claim 1 wherein said information handling system comprises a mainframe computer.
 18. The invention of claim 1 wherein said information handling system comprises a computer server. 